The following patent applications and patents, all of which were filed on Oct. 1, 1997 and were commonly owned, are hereby incorporated herein in their entirety by reference thereto:
The benefit under 35 U.S.C. xc2xa7 119(e) of the following U.S. provisional application(s) is hereby claimed:
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
1. Field of the Invention
The invention relates to interfaces between communication buses in electronic systems. Additionally, the invention relates to an interface between two buses in a computer system.
2. Description of the Related Technology
In the electronics industry, and more particularly in the computer industry, various bus architectures are used to permit parts of computer systems, multiple processors, and controllers to communicate. However, different bus architectures which are governed by different standards are frequently used within a single overall system. Therefore, there is a continuing need to develop interface methods and systems to permit communication between different buses.
One such bus architecture is the Inter-IC control bus (I2C bus). The I2C bus is a bi-directional two-wire bus (a serial data line and a serial clock line). Advantages of the I2C bus architecture are that it provides flexibility and lowers interconnecting costs by reducing board space and pin count. The I2C bus has particular application in video cards for computer systems and electronic components such as television tuners, AM/FM tuners, video decoders, video encoders, television audio decoders and video cross bars).
Another common bus architecture is the Industry Standard Architecture (ISA bus). The ISA bus is commonly used in computer systems to transfer data to and from the central processing unit or units.
There is a need for a method and apparatus for interfacing an I2C with an ISA bus. Such an interface would permit a CPU in a computer system to communicate with devices interconnected over an I2C bus.
The invention addresses the above and other needs by providing an interface apparatus and method, which in one embodiment includes a system interface processor coupled to a first bus and including a command register accessible via a second bus. A request buffer and a response buffer are provided which are accessible via the second bus and coupled to the interface processor. The request buffer can be used to store information to be transmitted from the second bus to the first via the interface processor while the response buffer can be used to store information to be transmitted from the first bus to the second bus via the interface processor. The interface processor may include a status register to indicate the status of the interface controller. The interface controller may also include a command register to receive commands transmitted over the second bus.